Process Management in Design Automation Front End

Electronic design automation starts with taking design specification in terms of English like language named Hardware Description Language(HDL). The examples are verilog, vhdl, system verilog like languages. To manage processes involved in parsing, elaborating and optimizing the design specified in HDL is a topic of discussion here and to be continued. Now, if we take a HDL parser from Verific or Interra to parse the RTL for rest part of the front end tool, it needs to be ensured that they provide consistent result. It is not very much intended that the parser gives incorrect or deviate from result across releases. It result the rest of the front end tools to also produce not so accurate  results. The process to be introduced is to validate any new release quickly before integration. The steps are Pre qualification, Qualification and Integration of release. Now what is pre qualification? Pre qualification is a quick step to identify any obvious flaws or result deviation from previous release. This may require to set up a short regresion. For parser pre qualification, it can run in 5-10 minutes. Qualification is a more thorough step, where the unit case and design results are verified. This can be some qa regression run and verify results.